1. Field of the Invention
The invention relates to a memory, and more particularly to a memory circuit.
2. Description of the Related Art
A memory circuit includes a plurality of memory cells for storing data. A memory circuit may operate in three different modes including an active mode, a sleep mode, and a power down mode. When the memory circuit operates in the active mode, data can be normally written to and read from the memory circuit, but the power consumption of the memory circuit is higher. When the memory circuit operates in the sleep mode, the power consumption of the memory circuit is reduced, the memory circuit can still keep data previously stored therein, but data can not be written to and read from the memory circuit. When the memory circuit operates in the power down mode, the power consumption of the memory circuit is further reduced, but the memory circuit cannot hold data previously stored therein.
Referring to FIG. 1A, a block diagram of a first conventional memory circuit 100 is shown. The conventional memory circuit 100 includes two PMOS transistors 101 and 102 and a memory array 110. The memory array 110 includes a plurality of memory cells for data storage. The area of the PMOS transistor 101 is larger than that of the PMOS transistor 102. The PMOS transistor 101 is coupled between a first voltage terminal VDD and a node 103, the PMOS transistor 102 is coupled between the voltage source VDD and the node 103, and the memory array 110 is coupled between the node 103 and a ground GND. When the memory circuit 100 operates in an active mode, an active signal turns on the PMOS transistor 101, and a sleep signal turns off the PMOS transistor 102. When the memory circuit 100 operates in a sleep mode, the sleep signal turns on the PMOS transistor 102, and the active signal turns off the PMOS transistor 101. When the memory circuit 100 operates in a power down mode, the active signal turns off the PMOS transistor 101, and the sleep signal turns off the PMOS transistor 102, cutting off the power supply to the memory circuit 100.
Because a power supply to a memory array of a conventional memory circuit is cut off in a power down mode, when an operating mode of the conventional memory circuit switches from the power down mode to an active mode, the voltages of all circuit components of the memory circuit must be charged to normal values of the active mode before the memory circuit can normally function in the active mode. Charging of the circuit component requires a large amount of power (referred to as a rushing power), and requires a long time period (referred to as wakeup time). When the operating mode of a memory circuit switches from a power down mode to an active mode, the large rushing power negatively impacts the performance of the memory circuit, and the long wakeup time also degrades the performance of the memory circuit.
To reduce the rushing power, a memory circuit 170 is shown in FIG. 1B. The memory circuit 170 includes a plurality of PMOS transistors 171, 172, . . . , 17n, and a plurality of delay elements 181, 182, . . . , 18(n−1). The PMOS transistors 171, 172, . . . , 17n are coupled between a first voltage terminal VDD and a node VVDD providing power to a memory array. When a sleep signal switches from a logic high voltage to a logic low voltage, the operating mode of the memory circuit switches from a sleep mode to an active mode, and the sleep signal is then fed to the gate of the first PMOS transistor 171 to turn on the first PMOS transistor 171. A delayed sleep signal is then fed to the gate of the second PMOS transistor 172 to turn on the second PMOS transistor 172. The PMOS transistors 171, 172, . . . , 17n are sequentially turned on to reduce a rushing power level. The wakeup time period of the memory circuit 170, however, is extended, degrading performance of the memory circuit 170. Thus, a memory circuit capable of switching an operating mode from a power down mode to an active mode with a lower rushing power and a shorter wakeup time period is required.